As the clock frequency increases at which integrated circuits, including microprocessor-based systems, operate, the clock period decreases such that there is less time available to accommodate board trace propagation delays in the clock signal. A high frequency clock signal is typically generated by a clock generation circuit using a low frequency crystal as an input reference clock signal. The clock generation circuit includes a frequency synthesizer to produce the high frequency clock signal output. The high frequency clock signal is routed through traces on a circuit board to devices such as a cache controller, processors, and random access memories. It is desirable to have clock signals arrive at all devices at precisely controlled times, which may be may not be simultaneous. The devices receiving the clock signal are located at various distances from the clock generation circuit resulting in traces of different length over which the clock signal must propagate. Differences in clock signal arrival time at various devices due to propagation delays, called clock skew, can be reduced but typically not eliminated by board layout. Furthermore, it is desirable to lay out a board efficiently to package as many components as possible into a given area with concerns over clock signal propagation delays addressed in another manner.
One solution to the clock propagation delay has been to provide a delay line clocked at a very high frequency. The output of the delay line is tapped at the number of delay elements through which it is desirable to propagate to obtain an appropriate delay. Additional resolution can be obtained by dividing down the tapped output to the desired frequency.
U.S. Pat. No. 5,126,691 discloses a similar solution in which a delay line is clocked at a very high frequency. The outputs of each stage in the delay are coupled to a multiplexer circuit that provides as an output the output, or the inverse of the output, of any of the delay stages. The output of the multiplexer is divided down to a desired frequency.
Delay line counter systems suffer from the drawback that delay line counters are inherently nonsymmetrical in propagation delay because the delay at each stage in the delay line is dependent on all previous stages. The higher a count, the greater the variation in delay relative to lower count delays. Furthermore, the increment of adjustment is limited to be multiples of the delay of each stage, as divided down by any counters. The delay is not dependent on the frequency but is the amount of time necessary for an input to propagate through the delay line.